1. Field of the Disclosure
The present disclosure relates to a circuit and an associated method for testing a chip, especially to a circuit and an associated method for testing a PLL (Phase Lock Loop) inside a chip.
2. Description of Related Art
A chip must pass a series of tests to verify its quality before sale. When a clock speed inside the chip plays an important part in the functionality of the chip, an at-speed test becomes one of the essential tests. Because a test machine nowadays can only provide limited test clock speeds, the use of the PLL inside the chip to generate a high-speed clock for the at-speed test is widely accepted. As a result, the accuracy in the at-speed test is highly dependent on the quality and condition of the clock generated by the PLL. In other words, a chip's failure in the at-speed test may result either from a defect of the chip itself or from imperfection of the test clock. For example, the clock generated by the PLL has a large jitter, or the frequency of the clock is not as expected because settings for the PLL are incorrect, or because a control signal that controls the PLL is subject to the test contents of the at-speed test. In addition, since the PLL is critical in providing an accurate working clock for the entire chip to work properly, a malfunction in the PLL can lead to unexpected errors.
Some prior-art methods are proposed to verify the clock generated by the PLL. Referring to FIG. 7, a test circuit disclosed in the U.S. Pat. No. 7,168,020 is presented. The test circuit includes a flip-flop 201, a flip-flop 202 and an XOR gate 203. The flip-flop 201 receives a PLL clock PLL_CLK and a sampling clock EXT_CLK. The frequency of the sampling clock EXT_CLK is twice the frequency of the PLL clock PLL_CLK. Therefore, the flip-flop 201 is trigged twice within one time period of the PLL clock PLL_CLK. As a result, the output signal SAMP of the flip-flop 201 has the same frequency as the PLL clock PLL_CLK. The flip-flop 202 receives the output signal SAMP of the flip-flop 201 and the sampling clock EXT_CLK, and generates an output signal SAMP_D1. The output signal SAMP_D1 has the same frequency as the output signal SAMP but is delayed by one time period of the sampling clock EXT_CLK, namely, half the time period of the PLL clock PLL_CLK. Therefore, there is a 180-degree phase difference between the output signal SAMP_D1 and the output signal SAMP. In other words, an output FAIL of the XOR gate 203 is at a high level when the PLL is in normal operation (i.e., the PLL clock PLL_CLK oscillating with a constant time period). The output signal SAMP and the output signal SAMP_D1 may be at a high level or a low level at the same time when the PLL is not in normal operation (i.e., the PLL clock PLL_CLK not oscillating or oscillating with an inconstant time period). A low-level output FAIL of the XOR gate 203 indicates that the PLL is not in normal operation. Although an abnormal operation of the PLL can be detected by the test circuit, the quality of the PLL clock and whether the abnormal operation is caused by false settings of the PLL cannot be known. In addition, the sampling clock EXT_CLK must be precisely controlled to slightly lead the PLL clock PLL_CLK to accurately sample the PLL clock PLL_CLK; such limitation increases the difficulty in practicing the test. Further, U.S. Pat. No. 8,040,995 discloses another test method, which uses a circuit for measuring jitters of a PLL clock. The circuit uses an oscillator to generate an oscillating signal whose frequency is a multiple of that of the PLL clock, and uses a counter to count the number of cycles of the oscillating signal in a count interval, in which the count interval is an integer multiple of the time period of the PLL clock. Then, the count result is analyzed to obtain the jitter information of the PLL clock. A shortcoming of this circuit is that the oscillator is so easily affected by manufacturing, voltage and temperature that the oscillating signal becomes unstable. Whenever there is a change in manufacturing, voltage and/or temperature, the measure result becomes inaccurate. In short, this circuit is not capable of determining how the temperature affects the PLL because the temperature has a greater influence on the reference clock (i.e., the oscillating signal) than on the PLL clock.